CITIC Securities: Nvidia GTC Set to Convene Soon, Four Key Highlights to Watch

NVIDIA GTC 2026 Conference is approaching, and the company’s chip product lineup is expected to expand further. In addition to the full set of six core chips for the Vera Rubin AI platform, more details about the Rubin Ultra chip and cabinet are likely to be disclosed at the conference, bringing innovations in data interconnection, power supply, and other architectural designs. The introduction of new products such as orthogonal backplanes and CPO is expected to become more visible. Meanwhile, NVIDIA may also release the LPU inference chip, which will expand its inference footprint alongside the CPX chip. Additionally, NVIDIA might outline the next-generation Feynman architecture upgrade, sharing insights and judgments on future computing infrastructure and the AI industry. The GTC 2026 is expected to further strengthen market confidence in the sustained growth of the AI industry and the realization of incremental logic.

Highlights 1: Rubin platform introduces a new chip combination, demonstrating extreme collaborative design

At CES 2026, NVIDIA announced the full set of six core chips for the Vera Rubin AI platform: Rubin GPU, Vera CPU, BlueField-4 DPU, NVLink 6 Switch, ConnectX-9 SuperNIC, Spectrum-6 Ethernet Switch. These components cover all major chips within the cabinet, all manufactured with TSMC’s 3nm process and equipped with HBM4 memory, with comprehensive upgrades in memory capacity and bandwidth. This product lineup enhances the synergy between GPU and CPU, as well as interconnect chips, with a modular design that makes the overall cabinet more cohesive compared to the previous Blackwell generation.

Highlights 2: More Rubin Ultra details expected, with architectural innovations in data interconnection and power supply

Since NVIDIA confirmed that the Vera Rubin platform has entered mass production at CES 2026, GTC 2026 may focus on revealing more details about Rubin Ultra chips and cabinets. Besides the chip itself, which doubles computing performance by integrating four compute dies, two major architectural directions are noteworthy:

1. Data interconnection: Significantly scaling up, the copper cable backplane scheme may be upgraded to a PCB orthogonal backplane (interconnecting compute and switch boards inside the canister) plus optical interconnects (intercabinet communication), forming a two-layer super network architecture. New processes/materials/products such as 78L RPCB, M9 CCL, Q glass electronics, and CPO are expected to be implemented.

2. Power supply system: Power delivery and energy consumption are increasingly limiting the expansion of computing infrastructure. Solutions like 800V high-voltage DC (HVDC) power systems and modular power supplies are expected to be adopted, potentially leading to upgrades in embedded PCB processes and GaN third-generation semiconductors.

Highlights 3: NVIDIA may unveil a new inference chip LPU to strengthen inference product line

NVIDIA is likely to elevate AI inference to a system-level infrastructure, with the LPU+CPX PD separation scheme enhancing the inference product line.

For LPU: At GTC, NVIDIA is expected to launch a new inference chip integrating Groq LPU technology, designed specifically for large language model (LLM) inference. It may feature a custom architecture with redesigned tensor streaming processors (TSP) and SRAM on-chip storage, greatly improving data storage and retrieval speeds, which is highly suitable for the high memory bandwidth demands of the decode stage.

For CPX: The Rubin CPX introduced in 2025 can effectively reduce prefill costs and may adopt GDDR7 or HBM3E as the main memory. According to SemiAnalysis, the product might shift from being integrated into the Rubin Compute Tray to a standalone cabinet supporting NVL72 VR200 shipments. Industry sources suggest that LPU could also be released as a 256-card LPX standalone cabinet.

Highlights 4: Outlook on the next-generation Feynman architecture upgrade

The design trend of NVIDIA’s next-generation Feynman architecture is gaining increasing industry attention, and NVIDIA may showcase related developments at GTC 2026. Based on current industry information, TrendForce predicts that Feynman will be among the first chips to adopt TSMC’s A16 process, with potential use of backside power delivery (SPR) to free up routing space, and possibly integrating 3D stacking technology for Groq’s LPU hardware stack. Production is expected to start around 2028, with deliveries to customers beginning in 2029. While specific details of Feynman remain unclear, NVIDIA’s understanding of future AI computing infrastructure upgrades will be crucial. In the context of Moore’s Law slowing down, how to support continuous AI industry iteration through innovations in computing power, storage, and operational capacity, and how the roles of training and inference evolve, as well as the outlook for AI investment return cycles, are likely to be key themes at GTC, inspiring and surprising the AI industry.

Risk Factors:

Macroeconomic fluctuations and geopolitical risks, slower-than-expected volume of new overseas computing products, continued rise in storage and component prices, technological changes and product iteration risks, policy regulation and data privacy concerns, and increased competition in the PCB industry.

Investment Strategy:

Focusing on the inflation of the computing chain, under the sustained demand for global computing power exceeding expectations, upstream sectors are expected to remain prosperous and see continued price increases. This remains the most certain “prosperity and growth” theme for current technology sector allocations. We are optimistic that GTC 2026 will further reinforce market confidence in the sustained growth and incremental logic realization of the AI industry.